Micron Details Next-Generation G11 NAND With Over 400 Layers and Wafer Bonding

Micron has outlined its next generation of 3D NAND flash, known as G11, which it expects to ramp in the second half of 2027. The company said at an event this week that the new memory will deliver roughly twice the storage density of its current technology, faster input/output performance and lower power consumption.

Compared with the existing G9 generation, G11 is expected to move from about 21 Gb/mm2 to about 42 Gb/mm2 in triple-level-cell form. Micron also projects I/O speeds rising by up to 50%, from 3,600 MT/s to 5,400 MT/s, while energy used to transfer each bit should fall by more than 25%. The density figure would represent a sizable jump over the next-generation NAND from rivals Kioxia (BiCS10) and Samsung (V10).

The gains are intended to benefit conventional high-capacity SSDs for client and data center use, as well as newer storage devices built for artificial intelligence workloads, which demand greater bandwidth and better energy efficiency.

A central change in G11 is the adoption of wafer-on-wafer bonding, an approach already used by Chinese rival YMTC. The method lets Micron build the NAND array and the peripheral circuitry and I/O on separate wafers, each made with a process suited to its job, and then bond the two together. Micron has used CMOS-under-array designs for several generations, but bonding gives it more freedom to optimize the memory array and the logic independently.

Scott DeBoer, Micron's president and chief technology and products officer, said the company had previously promised to introduce the technology when it became cost-effective and relevant to product specifications. "This is the right timing for that technology," he said, calling G11 "the world's most advanced NAND" and confirming it is based on wafer-on-wafer bonding.

G11 will also move past 400 layers. Micron has not revealed the exact number of active wordline layers or memory decks, but says the design will have an industry-leading memory cell pitch. That suggests the density improvement will come from a combination of additional layers and smaller cell dimensions. The company expects to share more technical details in 2027, closer to the start of high-volume production.

Looking beyond G11, Micron says it will keep scaling in all three dimensions rather than relying on layer count alone. It is developing what it calls breakthrough high-mobility materials, ultra-dense cell architectures and more energy-efficient devices and data paths, which could improve transistor characteristics, allow smaller cells and cut the energy needed to move data inside NAND chips.

"Beyond G11, we have a strong roadmap, not going to go into great detail on it today," DeBoer said, adding that the focus is on new materials, densifying the cell architecture and continued XYZ scaling. He noted that both the industry and Micron are scaling by adding layers and shrinking cell dimensions.

Micron has not disclosed architectural specifics, density targets or production schedules for generations after G11. Because adding layers remains one of the simplest ways to raise density, and demand for NAND-based storage is strong, the race for higher layer counts is not expected to slow significantly in the coming years.